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Features
* * * * * * * * * * * *
Digital Self-supervising Watchdog with Hysteresis Three 250-mA Output Drivers One Relay Driver, Two Lamp Drivers Lamp Drivers With Auxiliary Ground Short-circuit-protected Lamp Drivers Lamp Drivers With Status Feedback Enable Output Overvoltage/Undervoltage Detection and Reset All Power Outputs Protected Against Standard Transients All Power Outputs Protected Against 40V Load Dump Lamp Drivers Automatically Activated if VS is Disconnected Lamp Drivers Automatically Activated Via AUX GND if Standard Ground is Disconnected
Fail-safe IC with Relay Driver and Lamp Driver ATA6809
1. Description
The ATA6809 is designed to support the fail-safe function of safety-critical systems such as ABS. It includes a relay driver, two independent short-circuit-protected lamp drivers which are supplied by redundant ground lines, two monitoring circuits for the lamp driver output voltage and output current, a watchdog controlled by an external RC network, and a reset circuit initiated by an overvoltage or undervoltage condition of the 5V supply providing a positive and a negative reset signal.
Rev. 4902A-AUTO-11/05
Figure 1-1.
Block Diagram
VS
LA1I LA2I RELI WDI
Digital input lamp 1 Digital input lamp 2 Digital input relay Digital input wd
Logic
Open-collector 250 mA lamp driver 1
LA1O
Short-circuit detection and temperature monitor
Temperature
Microcontroller
FBLA1 FBLA2
Watchdog
Feedback lamp 1 Feedback lamp 2
Open-collector 250 mA lamp driver 2
LA2O
Loads
Debouncing of over- and undervoltage detection Oscillator monitoring RC-oscillator
Open-collector 250 mA relay driver
RELO
PRES NRES
p reset n reset
Open-collector 25 mA enable driver
ENO
OSC
GND
AUX GND
2. Pin Configuration
Figure 2-1. Pinning SO20
REL1 LA1I LA2I RELO GND GND FBLA1 NRES PRES FBLA2 1 2 3 4 5 6 7 8 9 10 20 WDI
19 VS 18 LA1O 17 GND 16 GND
ATA6809
15 GND 14 LA2O 13 AUX GND 12 ENO 11 OSC
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Table 2-1.
Pin 1 2 3 4 5, 6 7 8 9 10 11 12 13 14 15, 16, 17 18 19 20
Pin Description
Name RELI LA1I LA2I RELO GND FBLA1 NRES PRES FBLA2 OSC ENO AUX, GND LA2O GND LA1O VS WDI Type Digital input Digital input Digital input Open-collector driver output Supply Digital output Digital output Digital output Digital output Analog input Open-collector output Supply Open-collector driver output Supply Open-collector driver output Supply Digital input Function Activation of relay driver Activation of lamp driver 1 Activation of lamp driver 2 Fail-safe relay driver Standard ground Feedback lamp 1 Negative reset signal Positive reset signal Feedback lamp 2 External RC for watchdog timer Watchdog disable output Auxiliary ground of lamp drivers Warning lamp driver Standard ground Warning lamp driver 5V supply Watchdog trigger signal Pulse sequence Driver off: --Driver on: L Driver off: --Driver on: L Watchdog ok: --Watchdog not ok: L See Table 3-1 on page 5 and Table 3-2 on page 5 Reset: L No reset: H Reset: H No reset: L See Table 3-1 on page 5 and Table 3-2 on page 5 Logic Driver on: L Driver off: H Driver off: L Driver on: H Driver off: L Driver on: H Driver off:--Driver on: L
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3. Detailed Block Diagram with External Components
Figure 3-1. Detailed Block Diagram
VS
19 V Ref 4 + -
Reset debouncing
Push pull R+ Push pull R-
9
+ PRES
Reset delay + V Ref 5 RELI 1 + Debouncing
8
- NRES V Batt
A Temperature shut down Push pull L1 VS
4 RELO
7
FBLA1 V Batt
LA1I
2 + -
Failure detection lamp 1
V Ref2 + C 18 LA1O V Ref3
LA2I
3 + Debouncing
+ -
VS
V Batt
WDI
20 V Ref 1 + A B C
Failure detection lamp 2
V Ref2 + D E 14 LA2O
D V Ref3 + -
VS
Watchdog Ground backup
GND AUX GND
E
11 OSC
Oscillator D Integrated oscillator Internal timing C Push pull L2 E 10 FBLA2
Short-circuit protection B 12 ENO
5 6 15 16 17 GND
13 AUX GND
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Table 3-1. Truth Table for Lamp Drivers and Lamp Feedback
Inputs Lamp Voltage 1 1 0 0 0 1 1 0 Lamp Current 0 1 1 0 1 1 0 0 Lamp Driver Current Off On On Off On On Off Off Outputs Lamp Current Off Off On On On Off Off On/off Feedback Lamp 1 1 0 0 0 1 1 1
Lamp (I) 0 0 0 0 1 1 1 1 Note:
Comment Output ok or open (internal pull-up) or shorted to VBatt Output shorted to VBatt and faulty input level Internal driver activated due to internal failure Output shorted to GND Output ok Output shorted to VBatt Internal driver deactivated due to internal failure or thermal shutdown Output shorted to GND or open
Lamp voltage is logic 1 if output voltage > threshold voltage detection Lamp voltage is logic 0 if output voltage < threshold voltage detection Lamp current is logic 1 if output current > threshold current detection Lamp current is logic 0 if output current < threshold current detection
Table 3-2.
Table of Fault Detection
Feedback Lamp
Condition Normal operation Lamp output shorted to GND Lamp output shorted to VBatt Lamp output open Feedback shorted to GND Feedback shorted to VS Lamp input shorted to GND Lamp input shorted to VS
Lamp Input is 0 (Lamp Off) 1 0 (= detection) 1 (= no detection) 1 (= no detection) 0 (= detection) 1 (= no detection) 1 (= no detection) 0 (= detection)
Lamp Input is 1 (Lamp On) 0 1 (= detection) 1 (= detection) 1 (= detection) 0 (= no detection) 1 (= detection) 1 (= detection) 0 (= no detection)
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4. Fail-safe Functions
A fail-safe IC has to maintain its monitoring function even if there is a fault condition at one of the pins (for example, a short circuit). This ensures that a microcontroller system is not brought into a critical status. A critical status is reached if the system is not able to actuate a warning lamp and switch off the relay. The following table shows fault conditions for different pins during which the IC still works as a fail-safe device.
Table 4-1.
Pin LA2O LA2I LA1O LA1I RELI WDI OSC
Table of Fault Condition
Short to VS LA2O partly on LA2O on Faulty feedback LA1O partly on LA1O on Faulty feedback Relay off Watchdog reset Watchdog reset Short to VBatt LA2O off LA2O on Faulty feedback LA1O off LA1O on Faulty feedback Relay off Watchdog reset Watchdog reset Short to GND LA2O on LA2O off Faulty feedback LA1O on LA1O off Faulty feedback Relay on Watchdog reset Watchdog reset Open Circuit LA2O off LA2O on Faulty feedback LA1O off LA1O on Faulty feedback Relay off Watchdog reset Watchdog reset
Function Short-circuit proof driver for warning lamp Digital input to activate warning lamp Short-circuit proof driver for warning lamp Digital input to activate warning lamp Digital input to activate the fail safe relay Watchdog trigger input Capacitor and resistor of watchdog
FBLA2 Digital feedback of warning lamp
FBLA1 Digital feedback of warning lamp
5. Description of the Watchdog
5.1 Abstract
The microcontroller is monitored by a digital window watchdog which accepts an incoming trigger signal of a constant frequency for correct operation. The frequency of the trigger signal can be varied in a broad range as the watchdog's time window is determined by external RC components. The following description refers to Figure 1-1 on page 2. Figure 5-1. Watchdog Block Diagram
RCOSC
Binary counter
Dual MUX
WDI
Slope detector
Up/down counter
RS-FF
WD-OK
RESET OSCERR
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5.2 WDI Input (Pin 20)
The microcontroller has to provide a trigger signal with the frequency fWDI, which is fed to the WDI input. A positive edge of fWDI detected by a slope detector resets the binary counter and also clocks the up/down counter. The up/down counter only counts from 0 to 3 or reverse. Each correct trigger increments the up/down counter by 1, each wrong trigger decrements it by 1. As soon as the counter reaches the count of 3 the RS flip-flop is set (see Figure 5-2). A missing incoming trigger signal is detected after 250 clocks of the internal watchdog frequency fRC (see "WD-OK Output" ) and resets the up/down counter directly.
5.3
RCOSC Input
The IC generates a time base (frequency fRC) independent from the microcontroller via external RC circuitry. The watchdog's time window refers to a frequency of RC = 100 x fWDI
5.4
Reset Input
During power-on and undervoltage/overvoltage detection, a reset signal is fed to this pin. It resets the watchdog timer and sets the initial state.
5.5
WD-OK Output
After the up/down counter has reached 3 (see the WD state diagram, Figure 5-2 on page 7), the RS flip-flop is set and the WD-OK output becomes logic 1. This information is available for the microcontroller at the open-collector output ENO. If, on the other hand, the up/down counter is decremented to 0, the RS flip-flop is reset, and the WD-OK output and the ENO output are disabled. The WD-OK output also controls a dual MUX stage which shifts the time window by one clock after a successful trigger, thus forming a hysteresis to provide stable conditions for the evaluation of the trigger signal "good" or "bad". The WD-OK signal is also reset if the watchdog counter is not reset after 250 clocks (missing trigger signal).
5.6
Watchdog State Diagram
Figure 5-2. Watchdog State Diagram
good Initial status bad bad O/F bad good 1/F good bad 2/F good 1/NF bad bad 3/NF 2/NF good good
In each block, the number represents the state of the counter. "F" or "NF" indicates the fault status of the counter. Fault status is indicated by "F" and no-fault status is indicated by "NF". When the watchdog is powered up initially, the counter starts at the 0/F block (initial state). "Good" indicates that a pulse has been received whose width resides within the timing window. "Bad" indicates that a pulse has been received whose width is either too short or too long.
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5.7
Watchdog Window Calculation
Example with recommended values Cosc = 3.3 nF (should preferably be 10%, NPO) Rosc = 39 k (may be 5%, Rosc < 100 k due to leakage current and humidity)
5.8
RC Oscillator
tWDC (s) = 10-3 x [Cosc (nF) x [(0.00078 x Rosc (k)) + 0.0005]] fWDC (Hz) = 1 / (tWDC)
5.9
Watchdog WDI
fWDI (Hz) = 0.01 x fWDC tWDC = 100 s -> fWDC = 10 kHz fWDI = 100Hz -> tWDI = 10 ms
5.9.1
WDI Pulse Width for Fault Detection After 3 Pulses Upper watchdog window Minimum: 169 / fWDC = 16.9 ms -> fWDC / 169 = 59.1Hz Maximum: 170 / fWDC = 17.0 ms -> fWDC / 170 = 58.8Hz Lower watchdog window Minimum: 79 / fWDC = 7.9 ms -> fWDC / 79 = 126.6Hz Maximum: 80 / fWDC = 8.0 ms -> fWDC / 80 = 125.0Hz
5.9.2
WDI Dropouts for Immediate Fault Detection Minimum: 250 / fWDC = 25 ms Maximum: 251 / fWDC = 25.1 ms
Figure 5-3.
Time/s
Watchdog Timing Diagram with Tolerances
79 / fWDC 80 / fWDC 169 / fWDC 170 / fWDC 250 / fWDC 251 / fWDC
Watchdog window update rate is good Update rate is too fast Update rate is either too fast or good Update rate is either too slow or good Update rate is too slow Update rate is either too slow or pulse has dropped out Pulse has dropped out
5.9.3
Remark to Reset Delay The duration of the overvoltage or undervoltage pulse determines the enable and reset output. A pulse duration shorter than the debounce time has no effect on the outputs. A pulse longer than the debounce time results in the first reset delay. If a pulse appears during this delay, a 2nd delay time is triggered. Therefore, the total reset delay time can be longer than specified in the datasheet.
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6. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage range AUX GND offset voltage to GND AUX GND offset current to GND Power dissipation VS = 5V; Tamb = 125 C Thermal resistance Junction temperature Ambient temperature range Storage temperature range Symbol VS VAUX IAUX Ptot Rthjc Tj Tamb Tstg Value -0.2 to +16 1.5 -600 700 25 150 -40 to +125 -55 to +155 Unit V V mA mW K/W C C C
7. Electrical Characteristics
VS = 5V, Tamb = -40 to +125C; reference pin is GND; fintern = 100 kHz + 50% - 45%, fWDC = 10 kHz 10%; fWDI = 100Hz
Parameters Supply Voltage Operation range general Operation range reset Supply Current Lamp driver on, relay off Lamp driver off, relay on Lamp driver off, relay off Auxiliary Ground (AUX GND) AUX GND offset voltage operation range AUX GND offset voltage to GND Detection low Detection high Resistance to VS Input current low Input current high Input voltage = 0V Input voltage = VS Tamb = -40 C Tamb = 90 C Tamb = 125 C IAUX = -600 mA -1.2 -0.65 -0.5 -1.7 -0.2 0.7 x VS 10 100 -5 1.2 1.0 0.8 3.0 0.2 x VS VS + 0.5V 40 550 5 V V V V V V k A A Tamb = -40 C Tamb = 125 C Tamb = -40 C Tamb = 125 C Tamb = -40 C Tamb = 125 C 40 35 25 20 15 10 mA mA mA mA mA mA VS VS 4.5 1.5 5.5 16.0 V V Test Conditions Symbol Min. Typ. Max. Unit
Digital Inputs (LA1I, LA2I, REL1 and WDI)
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7. Electrical Characteristics (Continued)
VS = 5V, Tamb = -40 to +125C; reference pin is GND; fintern = 100 kHz + 50% - 45%, fWDC = 10 kHz 10%; fWDI = 100Hz
Parameters Voltage low Voltage high 10A I 1.6 mA Threshold voltage detection Threshold current detection Digital Outputs (PRES and NRES) Voltage high Voltage low Saturation voltage low Clamping voltage Current limit low Leakage current VENO = 5V VENO = 16V VENO = 26V I 125 mA; VS = 5V I 125 mA; VS = 0V I 250 mA; VS = 5V I 250 mA; VS = 0V I 250 mA; no GND Tamb = 90 C Tamb = 125 C VLA1O, LA2O = 16V VLA1O, LA2O = 26V 0.5 2 I 250 mA Tamb = 90 C Tamb = 125 C VBatt = 16V VBatt = 26V 250 200 26 30 20 200 250 180 26 30 1 3 1.0 17 0.5 I 100A I 1 mA I 25 mA 0.7 x VS + 0.1 0 0 26 25 20 100 200 0.5 1.5 1.0 2.0 3.0 VS 0.3 0.3 30 V V V V mA A A A V V V V V mA mA V mA mA A k V mA mA V A A Test Conditions I 1.6 mA I 10A Symbol Min. 0 0.8 x VS 0.7 x VS + 0.1 0.4 x VS 10 Typ. Max. 0.5 VS 0.5 x VS 50 Unit V V V mA Digital Outputs; Lamp Driver Feedbacks (FBLA1, FBLA2)
Digital Output (ENO) with Open Collector
Lamp Drivers (LA1O and LA2O) with Integrated Pull-up Resistor Saturation voltage Saturation voltage 250 mA requires enhanced heat sink Maximum load current Clamping voltage Leakage current Threshold current limitation Pull-up resistor Relay Driver (RELO) Saturation voltage Maximum load current Clamping voltage Leakage current
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7. Electrical Characteristics (Continued)
VS = 5V, Tamb = -40 to +125C; reference pin is GND; fintern = 100 kHz + 50% - 45%, fWDC = 10 kHz 10%; fWDI = 100Hz
Parameters Reset and VS Control Lower reset level Upper reset level Hysteresis Reset debounce time Reset delay Watchdog Timing Feedback reaction time (FBLA1, FBLA2) Minimum lamp input toggle time for a secure feedback reaction Power-on-reset prolongation time Detection time for RC-oscillator fault Time interval for overvoltage/ undervoltage detection Reaction time of NRES output on overvoltage/undervoltage Minimum toggle time for a secure broken ground detection Maximum reaction time for broken ground detection Nominal frequency for WDI Nominal frequency for RC Minimum pulse duration for a secure WDI input pulse detection Frequency range for a correct WDI signal Number of incorrect WDI trigger counts for locking the outputs Number of correct WDI trigger counts for releasing the outputs Detection time for a stuck WDI signal Watchdog Timing Relative to fRC Minimum pulse duration for a securely WDI input pulse detection Frequency range for a correct WDI signal Hysteresis range at the WDI ok margins Detection time for a stuck WDI signal VWDI = constant 250 80 1 251 2 170 cycles cycles cycle cycles VWDI = constant fRC = 100 x fWDI fWDI = 1 / 100 x fRC VRC = constant No fault, edge at LA1I, LA2I No fault, pulse at LA1I, LA2I tFB tP,FB tPOR tRCerror tD,OUV tR,OUV tP,BGND tR,BGND fWDI fRC tP,WDI fWDI nlock nrelease tWDIerror 24.5 10 1 182 64.7 3 3 25.5 ms 112.5 2.56 10.24 34.3 81.9 0.16 0.187 13.3 100 130 13 103.1 246 0.64 0.72 12.8 ms ms ms ms ms ms s s Hz kHz s Hz VS VS 4.5 5.2 25 120 20 500 80 4.8 5.5 V V mV s ms Test Conditions Symbol Min. Typ. Max. Unit
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Table 7-1.
Pulse 1 2 3a 3b 5 Note:
Protection Against Transient Voltages According to ISO TR 7637-3 Level 4 (Except Pulse 5)
Voltage -110V +110V -160V +150V 40V Source Resistance(1) 10 10 50 50 2 Rise Time 100V/s 100V/s 30V/ns 20V/ns 10V/ms Duration 2 ms 0.05 ms 0.1s 0.1s 250 ms Amount 15.000 15.000 1h 1h 20
1. Lamp drivers: 1.2 lamps need to be added to the source resistance. Relay driver: relay coil with Rmin = 70 need to be added to the source resistance.
7.1
Application Hints
a.) The lamp output pins LA1O and LA2O may need to be protected by external protection diodes (for example, BAV 202) against reversed battery, in order to avoid a reset during negative pulses. If pilot lamps with a wattage of P > 1.2W are connected, external Zener diodes are mandatory.
b.)
8. Timing Diagrams
Figure 8-1. Watchdog in Too Fast Condition
Normal operation 5V WDI 0V VBatt RELO 0V 5V ENO 0V VBatt LAXO 0V Don't care WDI too fast Normal operation
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Figure 8-2. Watchdog in Too Slow Condition
Normal operation 5V WDI 0V VBatt RELO 0V 5V ENO 0V VBatt LAXO 0V Don't care WDI too low Normal operation
Figure 8-3.
Overvoltage Condition
Overvoltage condition > 120 s 5.5 V 5V VS 0V V Batt RELO 0V 5V ENO 0V 5V NRES 0V V Batt LAXO 0V Reset debounce time 1st Reset delay 2nd Reset delay 3 good WDI pulses Don't care 5.5 V < 120 s
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Figure 8-4.
Undervoltage Condition
Undervoltage condition > 120 s 5V VS 0V V Batt RELO 0V 5V ENO 0V 5V NRES 0V V Batt LAXO 0V Reset debounce time 1st Reset delay 2nd Reset delay 3 good WDI pulses Don't care 4.5 V < 120 s 4.5 V
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9. Ordering Information
Extended Type Number ATA6809-TGQY Package SO20 special lead frame Remarks Taped and reeled, Pb-free
10. Package Information
Package SO20
Dimensions in mm
12.95 12.70 9.15 8.65 7.5 7.3
2.35 0.25 10.50 10.20 11
0.4 1.27 11.43 20
0.25 0.10
technical drawings according to DIN specifications
1
10
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